In some architectures, the execution stage of the pipeline must always be performing an action at every cycle. Such an event is often called a bubble, by analogy with an air bubble in a fluid pipe. The values are preserved until the instruction causing the conflict has passed through the execution stage. In a Von Neumann architecture which uses the program counter (PC) register to determine the current instruction being fetched in the pipeline, to prevent new instructions from being fetched when an instruction in the decoding stage has been stalled, the value in the PC register and the instruction in the fetch stage are preserved to prevent changes. It also stalls the instruction in the fetch stage, to prevent the instruction in that stage from being overwritten by the next instruction in the program. If this condition holds, the control unit will stall the instruction by one clock cycle. In a standard five-stage pipeline, during the decoding stage, the control unit will determine whether the decoded instruction reads from a register to which the currently executed instruction writes. In the design of pipelined computer processors, a pipeline stall is a delay in execution of an instruction in order to resolve a hazard. JSTOR ( August 2012) ( Learn how and when to remove this template message).Unsourced material may be challenged and removed. Please help improve this article by adding citations to reliable sources. This article needs additional citations for verification.
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